IBM… Details New Nanosheet Transistors for 5nm Chips
IBM and its Research Alliance partners, including GLOBALFOUNDRIES and Samsung announced that they have developed an industry-first process for building silicon nanosheet transistors that will enable 5 nanometer (nm) chips. Microprocessors manufactured with this process will incorporate as many as 30B switches on a fingernail sized chip, half again as many as the 7nm/20B transistor chips the Alliance announced less than two years ago.
Scientists at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY who work with the alliance used stacks of silicon nanosheets as the transistor device structure. This breakthrough design can replace the standard FinFET architecture the semiconductor industry has used up through existing 7nm node technologies.
The Alliance-led effort is the first to demonstrate the feasibility of designing and fabricating stacked nanosheet devices that support electrical properties superior to FinFET. It also successfully extends the exploratory work in nanosheet semiconductor technologies that IBM has pursued for over a decade.
According to IBM, compared to existing leading-edge 10nm chips, nanosheet-based 5nm technologies can deliver as much as 40 percent performance enhancements at fixed power, or 75 percent power savings at matched performance.
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NOTE: This column was originally published in the Pund-IT Review.